In a manufacturing process of an electronic device such as a MOS transistor, plasma etching of a polycrystalline silicon layer is performed. Plasma etching of a polycrystalline silicon layer is described in, for example, Patent Document 1. To be specific, Patent Document 1 describes that a polycrystalline silicon layer is etched by exciting a mixed gas containing a HBr gas, a Cl2 gas, and an Ar gas.
Further, a fin-type field effect transistor has been known as a kind of electronic device. The fin-type field effect transistor includes multiple fin regions made of silicon. The multiple fin regions are arranged on a substrate, and a gate electrode is provided to cover the fin regions. Regarding the gate electrode, metal materials having different work functions may be used as a N-type transistor and a P-type transistor. In a manufacturing process of a device, such as the fin-type field effect transistor, in which metal material is buried, a metal layer, such as a TiN layer, is formed on the fin regions, and polycrystalline silicon formed on the metal layer is etched. Then, the metal material is buried in a region from which the polycrystalline silicon is removed.
Patent Document 1: International Publication No. WO2009/028480
In the above-described manufacturing process of the fin-type field effect transistor, a polycrystalline silicon layer present at a fine gap, e.g., between adjacent fin regions, needs to be removed by etching, and damage to the metal layer caused by the etching needs to be suppressed.